Different retiming transformation technique to design optimized low power VLSI architecture

Jalaja S; Vijaya Prakash A M; Jalaja S; Vijaya Prakash A M

doi:10.3934/ElectrEng.2018.4.117

AIMS Electronics and Electrical Engineering

2018, Volume 2, Issue 4: 117-130. doi: 10.3934/ElectrEng.2018.4.117

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Research article

Different retiming transformation technique to design optimized low power VLSI architecture

Jalaja S ^{1
,
,},
Vijaya Prakash A M ²

1.
Department of Electronics and Communication, Research Scholar, Visvesvaraya Technological University, Bangalore Institute of Technology, Bangalore, India
2.
Department of Electronics and Communication, Bangalore Institute of Technology, Bangalore, India

Received: 06 September 2018 Accepted: 14 November 2018 Published: 26 November 2018

A different method for designing low power retime architecture is presented in this paper. The modified retiming transformation techniques approach to reduce the dynamic power consumption of the digital circuit, without compromising the output results. In this paper, retiming transformation is extended in two-ways to reduce the power consumption of the design. Graphical Circular Retiming and Tabular Shift Retiming are the two methods used to realize how the registers are mapped to reduce the glitching power. Proposed transformation technique delay value is placed in the form of metric and verified without sacrificing the functionality. Proposed transformation technique is applied to FIR filter to analyze the simulation and synthesis results as proofs of this concept. Experimental results are compared with the conventional retiming transformation technique with the same operating frequency, and with the significant reduction in dynamic power of FIR filter.
- graphical retiming transformation,
- tabular retiming transformation,
- reduction in dynamic power
Citation: Jalaja S, Vijaya Prakash A M. Different retiming transformation technique to design optimized low power VLSI architecture[J]. AIMS Electronics and Electrical Engineering, 2018, 2(4): 117-130. doi: 10.3934/ElectrEng.2018.4.117

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Abstract

A different method for designing low power retime architecture is presented in this paper. The modified retiming transformation techniques approach to reduce the dynamic power consumption of the digital circuit, without compromising the output results. In this paper, retiming transformation is extended in two-ways to reduce the power consumption of the design. Graphical Circular Retiming and Tabular Shift Retiming are the two methods used to realize how the registers are mapped to reduce the glitching power. Proposed transformation technique delay value is placed in the form of metric and verified without sacrificing the functionality. Proposed transformation technique is applied to FIR filter to analyze the simulation and synthesis results as proofs of this concept. Experimental results are compared with the conventional retiming transformation technique with the same operating frequency, and with the significant reduction in dynamic power of FIR filter.

References

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