1. Introduction

Power supply voltage drop (IR-drop) has been one of most important challenges of power interconnects in sub nanometer designs ^[1,2,3,4]. It becomes even more challenging for the high density and high performance designs in which it has adverse effects on timing. The increase in chip operating temperature has two-fold effects on timing. Firstly, it increases the interconnect resistance which in turn increases the interconnect delay. Secondly, due to the increase in resistance there is more IR-drop which also increases the gate delay. Therefore, it is very essential to analyze the effects of temperature on IR-drop in sub nanometer designs, since the resistivity of the traditional copper based interconnects increases significantly in nanometer dimensions ^[5]. GNR is one of the most promising material for interconnect modeling for future generation technologies ^[5,6] due to its excellent properties compared with copper in nanometer dimensions. Recent studies ^[6,7,8,9,10] on GNR show its superiority over the traditional copper based interconnects. The compact resistance modeling with only absolute temperature (300 K) in MLGNR stacks is proposed by Sansiri Tanachutiwat et al. reported in ^[11]. The temperature independent IR-Drop induced delay-fault model and simultaneous switching noise for MLGNR interconnects has been investigated by D. Das et al. reported in ^[12,13,14]. The temperature dependent comparisons of delay between CNT and Cu have been investigated in ^[15,16]. However, as per our knowledge no investigation has been carried out to analyze the effects of the temperature on IR-drop in multi layer graphene nanoribbon (MLGNR) interconnect till date. Motivated by the previous work, we have proposed a temperature dependent resistive model of multi layer graphene nanoribbon (MLGNR) interconnect. Using the proposed model, we have analyzed the power supply voltage drop (IR-drop) and delay in MLGNR based power interconnects. The rest of the paper is organized as follows. Section 2 and 3 presents the proposed temperature dependent resistive model of MLGNR and Cu interconnect. The results and conclusions are presented in the Sections 4 and 5.

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2. Temperature Dependent Resistance Model of MLGNR Interconnect

A multilayer GNR (MLGNR) structure is shown in Figure 1 is used for modeling power interconnects in nanoscale design. The width, thickness, and height of the MLGNR structure are denoted by w, t, and ht, respectively. The separation between two MLGNR structures is denoted by sp. In our interconnect design, we have considered width (w)=16 nm and thickness (t)=32 nm for 16 nm International technology roadmap for semiconductors (ITRS) technology node ^[5]. The total number of SLGNR present in proposed MLGNR structure is given by ^[7].

${N_{layer}} = 1 + Integer\left[{t/\delta } \right]$

(1)

The interlayer spacing (δ) between two consecutive graphene layers is 0.34 nm which is called as van der walls gap. Using (1) we obtain the total number of SLGNR present in proposed MLGNR structure as N_layer=95 for 16 nm technology node. The total resistance of MLGNR is given by.

${R_{Total - MLGNR}} = {R_Q}(1 + \frac{{{l_{MLGNR}}}}{{{\lambda _{effective}}}}) + {R_c}$

(2)

where l_MLGNR is the length of MLGNR based interconnect and λ_effective is the effective electron mean free path (MFP) of MLGNR. The quantum resistance (R_Q) of SLGNR is 12.94 kΩ. The contact resistance is assumed as 100 Ω·µm. The quantum resistance for MLGNR expressed as ^[7]

${R_Q} = \frac{{h/2.{e^2}}}{{{N_{ch}}.{N_{layer}}}} = \frac{{12.94 k\Omega }}{{{N_{ch}}.{N_{layer}}}}$

(3)

In (3) N_ch is the number of conducting channels in SLGNR, N_layer is the number of layer present in MLGNR, h is the Planck’s constant, and e is the electronic charge. The number of conducting channel present in SLGNR is given by ^[8,10]

${N_{ch}} = \sum\limits_{j = 1}^{{n_c}} {} {[1 + {e^{({E_{j,n}} - {E_F})/{k_B}T}}]^{ - 1}} + \sum\limits_{j = 1}^{{n_c}} {} {[1 + {e^{({E_F} + {E_{j,h}})/{k_B}T}}]^{ - 1}}$

(4)

where j=(1, 2, 3, …) is a positive integer, E_F is Fermi energy, k_B is the Boltzmann’s constant, T is temperature, and n_c and n_v are the number of conduction and valance sub-bands. E_{j, n} and E_{j, h} are the minimum energy of electron and hole in j_th conduction sub-band as given by ^[8]

${E_j} = \Delta E\left| {j + \beta } \right| ,\quad \text{where} \quad \Delta E = \frac{{h{v_f}}}{{2w}}$

(5)

ΔE is the sub-band energy in metallic GNR and β value is zero for metallic GNR and it is 1/3 in semiconducting GNR ^[8,10]. The Fermi potential for metallic GNR has been consider between 0.21 eV to 0.4 eV reported in ^[8,10]. The Fermi potential may varies in stacked multilayered GNR in each layer. Therefore, the value of Fermi energy for the inner layer GNR is derived as ^[11].

${E_{F,m}} = {E_F}{e^{ - \delta m/\Psi }}$

(6)

In (6), “m” is the position of the layer in stacked MLGNR structure, δ=0.34 nm and Ψ=0.387 nm is the fitting parameter reported in ^[11]. The average of all Fermi potential for top, bottom and inner layers (total Nlayer ≅ 95) is equal to 0.3 eV. The number of conducting channels (N_ch) is 6 for metallic SLGNR of width 16 nm for E_F=0.3 eV. The effective MFP of SLGNR interconnects depends on three important parameters: electron-electron scattering (λ_e), acoustic phonon scattering (λ_ap) and remote interfacial phonon scattering (λ_rip). Electron-electron scattering independent with temperature variation, but remaining two parameters vary with temperature which adversely affects on the interconnect delay due to change in resistance followed by temperature variation. Th e electron-electron scattering λ_e can be expressed as ^[11]

${\lambda _e} = {\lambda _{defect}} + w\sum\limits_{i = 1}^{{N_{ch}}} {} \sqrt {\frac{{{N_{ch}}}}{i} - 1}$

(7)

where, λ_defect is the MFP of SLGNR due to the defects exists inside the graphene layer. Here, “i” is an integer variable which varies from 1 to N_ch=6 and “w” is the interconnect width of MLGNR interconnect. The value of λ_defect is assumed to be 1 µm ^[11]. The MFP due to acoustic phonon scattering λ_ap can be expressed as ^[11]

${\lambda _{ap}} = \frac{{{h^2}{\rho _s}{v_s}^2{v_f}^2w}}{{{\pi ^2}D_A^2{k_B}T}}$

(8)

In (8), v_f is the Fermi velocity of GNR (=8 × 10⁵ m/s), v_s is the sound velocity of GNR (=2.1 × 10⁴ m/s), D_A is the acoustic deformation potential, k_B is the Boltzmann constant, ρ_s is the 2D mass density of graphene, and T is the temperature. The MFP due to remote interfacial phonon scattering λ_rip is expressed as ^[11]

${\lambda _{rip}} = \alpha E_F^{1.02}w({e^{\frac{{{E_0}}}{{kT}}}} - 1)$

(9)

where α is the fitting parameter, E_F is the Fermi potential, and E₀=104 mV. The temperature dependent effective MFP of SLGNR is given by applying Matthiessen’s rule ^[11]

${\lambda _{effective}} = {[{({\lambda _e})^{ - 1}} + {({\lambda _{ap}})^{ - 1}} + {({\lambda _{rip}})^{ - 1}}]^{ - 1}}$

(10)

The values of λ_e, λ_ap, λ_rip, and λ_effective, for different temperature are shown in Figure 2. Substituting the effective MFP of SLGNR in (2) we obtain the temperature dependent resistance of MLGNR in (11). The temperature dependent resistance values for different length and different temperatures for GNR interconnect is shown in Figure 3.

${R_{Total - MLGNR}} = {R_Q}\left[{1 + \frac{{{l_{MLGNR}}({\lambda _e}{\lambda _{ap}} + {\lambda _{ap}}{\lambda _{rip}} + {\lambda _{rip}}{\lambda _e})}}{{({\lambda _e}{\lambda _{ap}}{\lambda _{rip}})}}} \right]$

(11)

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3. Temperature Dependent Resistance Model of Cu Interconnect

The temperature dependent resistive model of Cu based nanointerconnect is explained in this section. To implement this model, surface roughness scattering and grain boundary scattering phenomena are considered. The surface roughness scattering based resistivity model first proposed by Fuchs ^[17] and Sondheim ^[18] (FS-model) which is given by (12)

$\frac{{{\rho _{FS}}}}{{{\rho _O}}} = 1 + \frac{3}{4}\frac{{{\lambda _O}}}{w}(1 - P)$

(12)

where ρ_o is the resistivity of the bulk material, w is width of the nanointerconnect, λ_o is the mean free path of the conduction electrons, and P (=0.6) is the Fuchs scattering parameter. The grain boundary scattering based resistivity model is proposed by Mayadas and Shatzkes (MS-model) ^[19] which is given by (13)

$\frac{{{\rho _{MS}}}}{{{\rho _O}}} = {\left[{1 - \frac{3}{2}\alpha + 3{\alpha ^2} - 3{\alpha ^3}\ln (1 + \frac{1}{\alpha })} \right]^{ - 1}}$

(13)

Where,

$\alpha = \frac{{{\lambda _O}}}{D}(\frac{R}{{1 - P}})$

Here D is the mean grain size and R is the reflection coefficient in the grain edges or boundaries with values in between 0 and 1. In our model, we have considered the mean grain size is equivalent to film width and R=0.33. The total resistivity of Cu nanointerconnect can be measured by combined effects of surface roughness and grain boundary scattering as given in (14)

${\rho _{Cu}} = {\rho _{FS}} + {\rho _{MS}}$

(14)

In (14) we have shown the temperature independent resistivity of Cu nanointerconnect. In general, the electrical resistivity of Cu nanointerconnects increases with temperature due to electron-phonon interactions mechanism ^[20]. As the temperature increase linearly, the resistance of Cu nanointerconnect also increases linearly. For Cu nanointerconnects, the temperature dependent resistivity ${\rho _{cu}}(T)$ follows a power law function of temperature which is given by the Bloch-Grüneisen model given in (15) ^[20,21,22]

${\rho _{Cu}}(T) = {\rho _{Cu}}(0) + 4R({\Theta _R}){\left[{\frac{T}{{{\Theta _R}}}} \right]^n}\int_0^{\frac{{{\Theta _R}}}{T}} {} \frac{{{x^n}}}{{({e^x} - 1)(1 - {e^{ - x}})}}dx$

(15)

Here,

$R({\Theta _R}) = \frac{\eta }{{{e^2}}}\left[{\frac{{{\pi ^3}{{(3{\pi ^2})}^{1/3}}{\eta ^2}}}{{4n_{cell}^{2/3}aM{k_B}{\Theta _R}}}} \right]$

${\Theta _R}$, is the Debye temperature used for resistivity calculation of Cu interconnect in nanometer dimension ^[20,21,22]. The Debye temperature ${\Theta _R}$, is taken ~320 K for bulk non-magnetic material like Cu ^[22]. In our analysis, the residual resistivity ${\rho _{Cu}}(0)$ in (15) has been ignored because it is temperature independent parameter and occurs due to presence of defect scattering ^[22]. Here $\eta$=Planck’s constant divided by 2π, n_cell=number of electron’s present in an atom which participate in current conduction, the atomic mass M=(atomic weight)/N_A, where N_A is the Avogadro’s number, a=(volume/atom)^1/3, k_B is Boltzmann’s constant, and e is the electron charge. Here “n” is an integer which depends on the characteristics of interaction. In general the value of “n” lies between 2-5.

1. n=5 signifies that the resistance variation is due to scattering of electrons by phonons (for simple metals like Cu) ^[23];

2. n=3 signifies that the resistance variation is due to s-d (spin density) electron scattering (for transition metals or dilute alloys) ^[23];

3. n=2 signifies that the resistance variation is due to electron-electron collisions or interaction. ^[23];

In our analysis we have considered the 1^st condition. Thus, the temperature dependent resistance of Cu nanointerconnect is given by (16)

${R_{Cu}}(T) = {\rho _{Cu}}(T).\frac{l}{{wt}}$

(16)

where l=length, w=width, and t=thickness of Cu nanointerconnect. Here “w” is 16 nm and “t” is 32 nm for 16 nm ITRS technology node for Cu interconnect same as MLGNR interconnect. Length of Cu nanointerconnect is varied from 10 µm to 100 µm. The temperature dependent resistance values of Cu nanointerconnect for different lengths at different temperature are shown in Figure 3.

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4. Results

Using the temperature dependent resistance model as discussed in previous section, we have calculated the resistance for different interconnect length and different temperature. In Figure 3 we have shown the temperature dependent resistance of MLGNR and Cu interconnect for different interconnect length (5 µm to 50 µm) for 16 nm technology node. MLGNR shows ~2-5x less resistance than that of Cu as shown in Figure 3. In Figure 2, with the increase in temperature, the effective mean free path reduces, and hence the scattering induced ohomic part of the total resistance of MLGNR increases. The IR-drop analysis is performed in MLGNR and Cu interconnects for 5 μm (local), 20 μm (intermediate) and 50 μm (global) interconnect lengths. The analysis is performed using equivalent circuit model shown in Figure 4.

In Figure 4, ten identical CMOS inverters are connected in series with temperature dependent resistance for both MLGNR and Cu. In our analysis, we have assumed the supply voltage as 0.7 V, the input voltage swing is from 0 to 0.7 V for all stages and pulse rise/fall time is assumed as 100 ps. The CMOS inverters are designed for 16 nm ITRS technology node using the Shttps://www.aimspress.com/aimspress-data/aimsmates/2016/4/PICE models from predictive technology model ^[24]. MOSFET model parameters are defined in Table 1. The simulations are performed using the Cadence spectra simulator. All the inverters are switched simultaneously so that they draw current from the power supply. As a result the power supply voltage decreases progressively away from the power pad. The decrease in power supply causes increase in propagation delay through the gate. As the temperature increases, the resistance of the power interconnects increases which causes more interconnect delay. With temperature as the IR-drop increases, the gates suffer more delay problem. Therefore, increase in temperature has twofold increase in delay: one due to increase in interconnect (RC) delay and the other due to increase in IR-drop. Figure 5-7 illustrate the IR-drop in GNR and Cu interconnects for local, intermediate, and global lengths. It is observed that the IR-drop increases with the increase in temperature both for MLGNR and Cu interconnects but MLGNR shows ~1.5-3.5× less IR-drop than Cu at local, intermediate and global lengths. The IR-Drop analyzed data shown in Table 2,Table 3 and Table 4, where maximum, minimum and average IR-Drop of MLGNR and Cu interconnects are present. The total propagation delay of MLGNR and Cu interconnect shown in Table 5. In our analysis, we also find out that MLGNR interconnect can reduce delay up to ~1.5-3× compared with Cu interconnect.

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5. Conclusions

In this work, we have proposed a temperature dependent resistive model of MLGNR and Cu interconnect and analyzed the effect of temperature on power supply voltage drop (IR-drop). It is observed that with the increase in temperature, the resistance is increased for both MLGNR and Cu, but MLGNR shows significantly less increase than the Cu interconnects ( ~2-5× times lesser), which exhibits less power supply voltage variation and hence less impact on the timing of the circuits. It also reduces the power dissipation of MLGNR based power interconnects as compared with Cu.

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Acknowledgments

This work is partially supported by the DIT, Government of West Bengal, India under VLSI Design Project.

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Conflict of Interest

The authors declare that there is no conflict of interest regarding the publication of this manuscript.

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