Implementation of on-chip high precision oscillators with RC and LC using digital compensation technique

1.   Introduction

In this research, we are primarily concerned with providing excellent and user-friendly medium- and high-frequency generators on a single chip. We anticipated incorporating RC and LC oscillators with different frequencies on a single chip. On-chip prepares for the most part to demonstrate network characteristics such as force utilization, area, speed, and cost. The crucial characteristic of an RC oscillator is its repetition strength ^[1]. Consideration is given to the repeatability of temperature variations and supply voltage variations. In the past, a balancing crossing out plan was used, which reduced temperature strength at low power. A self-isolated oscillator is used for steady clock output. This has the disadvantages of susceptible stage upheaval and high reaction time as a result of restricted bandwidth. Traded capacitor aggregated data is utilized to construct the oscillator's tenacity and reduce the glimmer noise ^[2]. A complementary cross coupled topology can be used to reduce the phase noise contribution due to the current noise sources ^[3]. The phase noise also can also be removed by automatic level control circuitry (ALC) in the micro mechanical regenerators ^[4]. Higher power consumption and more areas are drawbacks of this method.

In previous research, the influence of compensation Frequency (t_comp) was reduced by varying the reference voltage in comparators using a technique known as voltage averaging input. The majority of basic integrator analysis circles employ these procedures to establish repetition sufficiency; nevertheless, it demands more power consumption. Ring oscillators repeat got circles. This may affect the benchmark. In FLL, a very low-power enhancer has an effect on the VCO when the temperature fluctuates. Feed forward approach in a detuned oscillator is used to reduce compensation frequency using a support charging scheme. Repeat pay systems can be used in similar manner. These strategies require more power. When designing an on-chip oscillator, it is difficult to ensure repeat stability against variations in temperature and voltage. Various types of resistors are used to reduce temperature coefficients ^[2]. Chopper techniques are employed to reduce the comparator's balance, as well as for voltage reduction. For high repeatability (in MHz), comparator delay is the limiting factor (tcomp), the tuning range of LC oscillator can be improved by incorporating dual LC oscillator instead of single band LC oscillator ^[5].

The required oscillator is chosen for low power and low-level disturbance: Comparing doorway coupling type and nearby transformer concentration. Consideration is given to a dual-band LC oscillator with two P-type FETs. A dual-band LC oscillator with a particular configuration in the LC tank and a self-resonating device is used. Two required cross-coupled and differential lift lashed inductors already have been reported. All of this prior research necessitated a center-tapped transformer with a high execution cost. Massive repeat generators are used to provide kHz repetition. On the RC and LC oscillator chip with 12 MHz and 30 GHz, it is suggested to reduce the aforementioned shortcomings. The schematics are shown in Figures 1 and 3. In the proposed work, CMOS LC push-push In an LC oscillator, VCO topography is utilized to enhance stage upheaval under low voltage movement. In order to avoid using various inductors, an LC tank with a PMOS push stage is used to replicate the repetition. Inductive switching method is commonly used strategy to design a switched LC VCO instead of capacitive to increase the quality factor ^[6]. The applicability of LC VCO is similar to oscillators used in broad-band transmission networks. Therefore, it is suggested integrating RC and LC oscillators with varying frequencies onto a single chip. This concept eliminates the need of enormous repetition generating equipment ^[7]. Temperature to Digital Converter (TDC) can be used in oscillator to reduce the temperature effect ^[8]. The proposed architecture can be used in MEMS for biomedical applications ^[9]. MEMS technology has been used as micro regenerators as vibrating cantilever beams which are well known as RF MEMS ^[10].

2.   Methodology

In the above circuit, there are three ammeters, one associated with a resistor and the other two associated with switches and capacitors. The two ammeters associated with switches and capacitors are directly connected to the comparator, which is used to separate the signals and produce a signal whose signal strength is high. The produced signal is connected to an SR flip-flop ^[7]. The RC oscillator's primary function is that of a stage shift oscillator. The circuit on the left consists of a single resistor-capacitor network whose yield voltage "drives" the data voltage by a little angle less than 90 degrees. In an unadulterated or perfect single-post RC association, it would make a stage change of no more than 90°, and because 180° of stage shift is essential for influencing, at least two single-posts organizations should be used in an RC oscillator plan ^[11].

3.   Reference pulse generator

Reference pulse is generated by reference voltage and comparator in the on-chip digital compensation technique. When the clock signal is high, the capacitor charges and generates a voltage Vmin connected to the positive terminal of comparator 1 (comp₁)

Vmax is connected to the negative terminal of the comparator 2 (comp₂). The time t₂ is expressed as

Pulse reference is given as

The difference between the two comparators is the reference pulse, wherein, the output of comparators is V₁ and V₂. In case of any non-ideal mismatch, the reference pulse is given as

V_os1 and V_os2 are offset voltages of comparators. The below waveforms represent the offset voltages V₁ and V₂ and reference pulse obtained by applying the clock pulse in the proposed RC oscillator ^[11]. For on-chip high precision RC and LC oscillators, the waveform obtained by the proposed relaxation oscillator is shown in Figure 2.

4.   Architecture of LC VCO

Cross-coupled LC VCO generates Ku band recurrence (12 to 18 GHz), as seen in the design above. Using a PMOS push-push frequency doubler with an inductor, Ku band frequency is converted to Ka-band frequency (26 to 40 GHz). This is carried out using 45 nm innovation and a 1.35 V supply voltage. To avoid additional inductors, a low band LC tank inductor is devised. Together, varactors and inductors form the LC tank. The differential PMOS recurrence doubler inclination current is repurposed as a bias for low band LC VCO. To compensate for the loss in the LC tank, the NMOS cross-coupled circuit is employed. The scope of the variable CV1 is modified by the V_cont. V_cont is used to provide a variable recurrence yield. A semiconductor with an integrated source, channel, and mass is considered while creating a design for a so-called varactor. CV1 L1 is used as a balancing to avoid lengthy interconnects and undesired RF signal and DC electrical cable transmission. Due to confusion and imbalance, stage variations and adequacy balances may arise ^[12]. To reduce this abundance, the necessary balances and stage circuit layout are created. In the schematic, L = 0.19 nH and C = 2 pf were considered.

From above specifications

By reducing the capacitance by four times, i.e., C = 2 pF, C1 = 0.5 pF, frequency is increased

Frequency switching in 8 times

All the MOSFETs are connected to capacitors and are controlled by a digital control that is the decoder. The inputs to the decoder are CTRL and IN. We can enhance the frequency by taking 16 steps that are reducing the capacitance by a factor of 16:

The above layout sub-blocks reference generator, 1 comp, 2 comp transmission gates and buffer as per the architecture of RC oscillator as shown in Figure 1 is integrated in Figure 4.

The layout of an inductor is designed as shown below. According to the schematic in Figure 3, the inductor is designed with an L = 0.19 nH width of 11 μm.

Inductance is developed by connecting two resistors in series as shown in Figure 6.

The layout of LC VCO is done in a symmetrical manner which is shown below. As LC VCO produces high frequency in terms of MHz, the floor plan of LC VCO is placed symmetrically ^[13].

I/O cells are utilized to link the core to the outside environment. Different I/O cells are utilized for pad limited and core limited. Filler cells are used to fill the space between adjacent pads. These filler cells are used to join the pads together. Filler cells are utilized to create a connection between two pads.

RC and LC oscillators are placed on a single chip which is controlled by I/O cells which are shown below. The oscillator is fabricated in a 45nm process which is shown in Figure 8.

Figure 9 shows the frequency versus impedance. The thick line curve is the frequency at 0 V voltage and the dotted line curve represents the frequency at 1.5 V voltage ^[13].

4.1.   Measurement results

Figures 10 represents the frequencies at 16.8 GHz and 32.67 GHz, respectively. These high frequencies in terms of GHz are generated by using an LC oscillator ^[14].

Figure 11 represents the frequency offset pf 112.3 at 32.67 GHz respectively. These high frequencies in terms of GHz are generated by using an LC oscillator ^[14].

Figure 12 represents the curve for output frequency across different supply voltages, the minimum frequency at 12 MHz at 0.4 Volts and the maximum frequency at 12.4 MHz at 1.2 Volts.

Table 1 represents the comparison of RC oscillator with various frequencies at different technology nodes where the proposed work gives provides the accurate results.

Table 2 represents the RC oscillator phase noise comparison at different technology nodes where the phase noise is positive due to its low offset at low frequencies.

5.   Conclusions

In this work, fully coordinated RC and LC VCO are implemented on a single chip on which the simulation is performed. The features of RC and LC VCO include a stable yield frequency of 12 MHz and 32 GHz, as well as a stage oscillation of 112.1@1MHz. Automated remuneration techniques are used to reduce power consumption and increase noise performance. A RC oscillator uses 12.8 W of power, but an LC oscillator uses 3 mW. This on-chip RC and LC oscillators are produced using 45 nm technologies. The frequency accuracy must be given in terms of the frequency accuracy of the reference oscillator or the frequency accuracy of the output. Typically, the parameters are represented in terms of frequency offset or frequency range from the ideal center frequency. Frequency drift is a long-lasting consequence. It was discovered that the suggested models are expertly crafted using nodes of modern technology. This on-chip oscillator is used in fully integrated system-on-chip systems that are governed by an internal voltage-controlled oscillator (VCO).

Conflict of interest

The authors declare that there is no conflict of interest.