Analytical models of threshold voltage and drain induced barrier lowering in junctionless cylindrical surrounding gate (JLCSG) MOSFET using stacked high-<i>k</i> oxide

Hakkee Jung; Hakkee Jung

doi:10.3934/electreng.2022007

AIMS Electronics and Electrical Engineering

2022, Volume 6, Issue 2: 108-123. doi: 10.3934/electreng.2022007

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Research article

Analytical models of threshold voltage and drain induced barrier lowering in junctionless cylindrical surrounding gate (JLCSG) MOSFET using stacked high-k oxide

Hakkee Jung ^,

Department of Electronic Eng., Kunsan National University, Gunsan-si, Jeollabuk-do, 54150, Republic of Korea

Received: 26 December 2021 Revised: 28 February 2022 Accepted: 11 March 2022 Published: 16 March 2022

We proposed the analytical models to analyze shifts in threshold voltage and drain induced barrier lowering (DIBL) when the stacked SiO₂/high-k dielectric was used as the oxide film of Junctionless Cylindrical Surrounding Gate (JLCSG) MOSFET. As a result of comparing the results of the presented model with those of TCAD, it was a good fit, thus proving the validity of the presented model. It could be found that the threshold voltage increased, but DIBL decreased by these models as the high-k dielectric constant increased. However, the shifts of threshold voltage and DIBL significantly decreased as the high-k dielectric constant increased. As for the degree of reduction, the channel length had a greater effect than the thickness of the high-k dielectric, and the shifts of threshold voltage and DIBL were kept almost constant when the high-k dielectric constant was 20 or higher. Therefore, the use of dielectrics such as HfO₂/ZrO₂, La₂O₃, and TiO₂ with a dielectric constant of 20 or more for stacked oxide will be advantageous in reducing the short channel effect. In conclusion, these models were able to sufficiently analyze the threshold voltage and DIBL.
- cylindrical surrounding gate,
- junctionless,
- threshold voltage,
- DIBL,
- stacked oxide,
- high-k
Citation: Hakkee Jung. Analytical models of threshold voltage and drain induced barrier lowering in junctionless cylindrical surrounding gate (JLCSG) MOSFET using stacked high-k oxide[J]. AIMS Electronics and Electrical Engineering, 2022, 6(2): 108-123. doi: 10.3934/electreng.2022007

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Abstract

We proposed the analytical models to analyze shifts in threshold voltage and drain induced barrier lowering (DIBL) when the stacked SiO₂/high-k dielectric was used as the oxide film of Junctionless Cylindrical Surrounding Gate (JLCSG) MOSFET. As a result of comparing the results of the presented model with those of TCAD, it was a good fit, thus proving the validity of the presented model. It could be found that the threshold voltage increased, but DIBL decreased by these models as the high-k dielectric constant increased. However, the shifts of threshold voltage and DIBL significantly decreased as the high-k dielectric constant increased. As for the degree of reduction, the channel length had a greater effect than the thickness of the high-k dielectric, and the shifts of threshold voltage and DIBL were kept almost constant when the high-k dielectric constant was 20 or higher. Therefore, the use of dielectrics such as HfO₂/ZrO₂, La₂O₃, and TiO₂ with a dielectric constant of 20 or more for stacked oxide will be advantageous in reducing the short channel effect. In conclusion, these models were able to sufficiently analyze the threshold voltage and DIBL.

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