An intelligent fault detection approach for digital integrated circuits through graph neural networks

Zulin Xu; Zulin Xu

doi:10.3934/mbe.2023438

Mathematical Biosciences and Engineering

2023, Volume 20, Issue 6: 9992-10006. doi: 10.3934/mbe.2023438

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Research article

An intelligent fault detection approach for digital integrated circuits through graph neural networks

Zulin Xu ^,

SDU-ANU Joint Science College, Shandong University, Shandong 264209, China

Received: 31 December 2022 Revised: 28 February 2023 Accepted: 02 March 2023 Published: 27 March 2023

To quickly and accurately realize the fault diagnosis of analog circuits, this paper introduces the graph neural network method and proposes a fault diagnosis method for digital integrated circuits. The method filters the signals present in the digital integrated circuit to remove noise signals and redundant signals and analyzes the digital integrated circuit characteristics after the filtering process to obtain the digital integrated circuit leakage current variation. To the problem of the lack of a parametric model for Through-Silicon Via (TSV) defect modeling, the method of TSV defect modeling based on finite element analysis is proposed. The common TSV defects such as voids, open circuits, leakage, and unaligned micro-pads are modeled and analyzed by using industrial-grade FEA tools Q3D and HFSS, and the equivalent circuit model of resistance inductance conductance capacitance (RLGC) for each defect is obtained. Finally, the superior performance of this paper in fault diagnosis accuracy and fault diagnosis efficiency is verified by comparing and analyzing with the traditional graph neural network method and random graph neural network method for active filter circuits.
- graph neural network,
- intelligent fault detection,
- digital integrated circuits,
- artificial intelligence
Citation: Zulin Xu. An intelligent fault detection approach for digital integrated circuits through graph neural networks[J]. Mathematical Biosciences and Engineering, 2023, 20(6): 9992-10006. doi: 10.3934/mbe.2023438

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Abstract

To quickly and accurately realize the fault diagnosis of analog circuits, this paper introduces the graph neural network method and proposes a fault diagnosis method for digital integrated circuits. The method filters the signals present in the digital integrated circuit to remove noise signals and redundant signals and analyzes the digital integrated circuit characteristics after the filtering process to obtain the digital integrated circuit leakage current variation. To the problem of the lack of a parametric model for Through-Silicon Via (TSV) defect modeling, the method of TSV defect modeling based on finite element analysis is proposed. The common TSV defects such as voids, open circuits, leakage, and unaligned micro-pads are modeled and analyzed by using industrial-grade FEA tools Q3D and HFSS, and the equivalent circuit model of resistance inductance conductance capacitance (RLGC) for each defect is obtained. Finally, the superior performance of this paper in fault diagnosis accuracy and fault diagnosis efficiency is verified by comparing and analyzing with the traditional graph neural network method and random graph neural network method for active filter circuits.

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